Cmsemicon CMS32L051 - Chapter 20 Standby Function; 20.1 Standby function

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CMS32L051 User Manual |Chapter 20 Standby Function
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Chapter 20 Standby Function
20.1 Standby function
The standby function is a function that further reduces the operating current of the system, and there are two
modes.
(1) Sleep mode
Sleep mode is the mode that stops the CPU from running the clock. Each clock continues to oscillate before
setting the sleep mode, such as if the high-speed system clock oscillation circuit, the high-speed internal oscillator, or
the subsystem clock oscillation circuit is oscillating. Although this mode does not allow the operating current to drop
to the level of deep sleep mode, it is an effective mode when you want to restart processing immediately with an
interrupt request or if you want to do intermittent operation frequently.
(2) Deep sleep mode
Deep sleep mode is a mode that stops the oscillation of the high-speed system clock oscillation circuit and the
high-speed internal oscillator and stops the entire system. It can greatly reduce the operating current of the CPU.
Because deep sleep mode can be released by interrupt requests, it can also be run intermittently. However, in
the case of the X1 clock, because the wait time to ensure oscillation stability is required when the deep sleep mode
is released, if you need to start processing immediately with an interrupt request, you must choose the sleep mode.
In deep sleep mode, except for partial power loss, registers, flags, and data memory all remain what was before
they were set to standby mode, and the output latches and output buffers of the input/output ports are also maintained.
Note 1 Deep sleep mode can only be used when the CPU is running at the main system clock. When the CPU is running
on the secondary system clock, it cannot be set to deep sleep mode. Sleep mode can be used regardless of
whether the CPU is running on the primary system clock or the secondary system clock.
2. When transferring to deep sleep mode, WFI instructions must be executed after stopping peripheral hardware
running at the main system clock.
3. To reduce the operating current of the A/D converter, the A/D converter mode register 0 (ADM0) must be placed at
bit7 (ADCS) and bit0 (ADCE) clear 0 and execute the WFI instruction after stopping the A/D conversion operation.
4. The option byte allows you to choose whether to continue or stop oscillating the low-speed internal oscillator in
sleep mode or deep sleep mode. For details, please refer to Chapter 26 Option Bytes.