Cmsemicon CMS32L051 - Processing Steps When an Error Occurs in a Simple I2 C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21); Communication Process

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CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.9.6 Processing steps when an error occurs in a simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,
IIC21) communication process
The processing steps when an error occurs during a simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)
communication are shown in Figure 12-130 and Figure 12-131.
Figure 12-130 Steps to handle when an overflow error occurs
Figure 12-131 Processing steps when an ACK error occurs in a simplified I
2
C mode
Remark m: Unit number (m=0, 1) n: Channel number (n=0~3) r: IIC numbers (r=00, 01, 10, 11, 20, 21 )
mn=00~03, 10~1.
Software operation
Hardware status
Remark
The BFF m n bit of the SSRm n register
is "0" and channel n is receivale.
This is to prevent overflow errors from
ending the next reception
during
mishandling.
Read serial status register mn(SSRmn).
The type of error is judged, and the
reading value is used to clear the error
flag.
Clear the error flag.
By writing the read value of the SSRmn
register directly to the SDIRmn register,
errors during read operations can only
be cleared.
Read serial data register mn
(SDRMN).
Write "1" to the serial flag clear
trigger register mn (SDIRmn).
Software operation
Hardware status
remark
Read the serial status register
mn(SSRmn)
.
Determine the error category, and read
the value to remove the error marker.
Clear the error flag.
By writing the read value of the SSRmn
register directly to the SDIRmn register,
errors during read operations can only
be cleared.
The SEmn bit of the Serial Channel
Enable Status Register m (SEm) is "0"
and channel n is running stop.
Because ACK is not returned, the slave
device is not ready for receiving. Thus,
a stop condition is generated and the
bus is released, and communication is
started again from the start bar, or a
restart can also be generated and start
again from the address to send.
Generate a stop condition.
Generate a start conditions
Set the serial channel start register m
(SSm) to
SSmn bit to "1".
The SEmn bit of the Serial Channel
Enable Status Register m (SEm) is "1"
and channel n is operational
Write the serial flag to clear
the trigger register mn
(SDIRmn)
。
Set the STmn bit of the serial
channel stop register m (STm) to
"1".