Cmsemicon CMS32L051 - Page 457

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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Table 12-5 Simplified I
2
C Running Clock Selection
SMRmn
register
SPSm register
Running clock (f
MCK
)
Note
CKSmn
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
f
CLK
=32MHz operation
0
X
X
X
X
0
0
0
0
f
CLK
32MHz
X
X
X
X
0
0
0
1
f
CLK
/2
16MHz
X
X
X
X
0
0
1
0
f
CLK
/2
2
8MHz
X
X
X
X
0
0
1
1
f
CLK
/2
3
4MHz
X
X
X
X
0
1
0
0
f
CLK
/2
4
2MHz
X
X
X
X
0
1
0
1
f
CLK
/2
5
1MHz
X
X
X
X
0
1
1
0
f
CLK
/2
6
500kHz
X
X
X
X
0
1
1
1
f
CLK
/2
7
250kHz
X
X
X
X
1
0
0
0
f
CLK
/2
8
125kHz
X
X
X
X
1
0
0
1
f
CLK
/2
9
62.5kHz
X
X
X
X
1
0
1
0
f
CLK
/2
10
31.25kHz
X
X
X
X
1
0
1
1
f
CLK
/2
11
15.63kHz
1
0
0
0
0
X
X
X
X
f
CLK
32MHz
0
0
0
1
X
X
X
X
f
CLK
/2
16MHz
0
0
1
0
X
X
X
X
f
CLK
/2
2
8MHz
0
0
1
1
X
X
X
X
f
CLK
/2
3
4MHz
0
1
0
0
X
X
X
X
f
CLK
/2
4
2MHz
0
1
0
1
X
X
X
X
f
CLK
/2
5
1MHz
0
1
1
0
X
X
X
X
f
CLK
/2
6
500kHz
0
1
1
1
X
X
X
X
f
CLK
/2
7
250kHz
1
0
0
0
X
X
X
X
f
CLK
/2
8
125kHz
1
0
0
1
X
X
X
X
f
CLK
/2
9
62.5kHz
1
0
1
0
X
X
X
X
f
CLK
/2
10
31.25kHz
1
0
1
1
X
X
X
X
f
CLK
/2
11
15.63kHz
Beyond the above
Disable settings.
Notice To change the clock selected as f
CLK
(change the value of the system clock control register (CKC)), you must
stop the operation of the universal serial communication unit (SCI) (serial channel stop register m( STm)=000FH)
after making the change.
Note 1.X: Ignore
2.m: Unit number (m=0, 1) n: channel number (n=0~3)mn=00~03 , 10~11.
An example of setting the I
2
C transfer rate at f
MCK
=f
CLK
=32MHz is shown below.
I
2C
transfer mode
(Expected transfer
rate)
f
CLK
=32MHz
Running clock (f
MCK
).
SDRmn[15:9]
Calculated transfer
rate
Error with expected
transfer rate
100kHz
f
CLK
/2
79
100kHz
0.0%
400kHz
f
CLK
41
380kHz
5.0%
Note
1MHz
f
CLK
18
0.84MHz
16.0%
Note
Note Because the duty cycle of the SCL signal is 50%, the error cannot be set to about 0%.