CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.2.1 Shift register
This is a 9-bit register that converts parallel and serial to and from each other.
For UART communication at 9 bits of data length, use 9 bits (bit0 to 8)
Note 1
. Converts the input data of
the serial input pin into parallel data when receiving data; When data is sent, the value to this register will be
transferred as serial data from the serial output pin output
Note 1
. Shift registers cannot be manipulated directly
through the program.
To read and write data from shift registers, use the low 8 or 9 bits of the serial data register mn (SDRmn).
12.2.2 Low 8 bits or low 9 bits of serial data register mn (SDRmn)
The SDRmn register is the transmit and receive data registers (16-bit) of channel n.
Bit8~0 (low 9 bits)
Note
or bit7~0 (low 8 bits) is used as the transmit and receive buffer registers bit15~9 is
used as a crossover setting register for the running clock (f
MCK
).
When receiving data, save the parallel data converted by the shift register to the lower 8 bits or the lower
9 bits; When transmitting data, the transmitted data to the shift register is set to a lower 8 bits or a low 9 bits.
Regardless of the output order of the data, set registers mn (SCRmn) bit0 and bit1 (DLSmn0, DLSmn1)
are run according to serial communication) settings saved to the lowest 8 bits or lower 9 bits of data as
follows:
7-bit data length (saved in bit0~6 of the SDRmn register).
8 bits of data length (saved in bit0~7 of the SDRmn register).
9 bits of data length (saved in bit0~8 of the SDRmn register)
Note 1
SDRmn registers can be read and written in 16-bit increments.
Depending on the communication mode, the low 8 bits of the SDRmn register or the low 9 bits of the
SDRmn register can be read and written in 8-bit units with the following SFR name
Note 2
.
•
SSPIp communication... SDIOp (SSPIp Data Register).
•
UARTq receives... RXDq (UARTq Receive Data Register).
•
UARTq sends... TXDq (UARTq Transmit Data Register).
•
IICr Communications... SDIOr (IICr Data Register).
After the reset signal is generated, the value of the SDRmn register changes to 0000H.
Note 1 Only UART0 supports 9-bit data length.
2. When the operation is stopped (SEmn=0), it is forbidden to override SDRmn [7:0] via 8-bit memory operation
instructions (otherwise, SDRmn [15:9] is cleared).
Note 1 After the reception ends, bits from bit0 to 8 that exceed the length of the data are 0.
2.m: Unit number (m=0, 1) n: channel number (n=0~3) p: SSPI number (p=00, 01, 10, 11, 20, 21)
q: UART number (q=0~2) r: IIC number (r=00, 01, 10, 11, 20, 21)
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