CMS32L051 User Manual |Chapter 14 Serial interface IICA
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14.6 Timing diagram
In I
2
C-bus mode, the master device selects a slave device for a communication object from multiple slave
devices by giving the serial bus output address. The master device sends the TRCn bit (bit3 of the IICA status
register n (IICSn)) indicating the direction of data transmission after the slave device address serial
communication with the slave begins. The timing diagram of the data communication is shown in Figure
14-31.
The IICA shift register n (IICAn) is synchronized with the falling edge of the serial clock (SCLAn) and the
transmitted data is transferred to the SO latch to the MSB Data is output from the SDAAn pin first.
The data input to the SDAAn pin is fetched to IICAn on the rising edge of SCLAn.
Note n=0
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