CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.7.3 Considerations when manipulating channel inputs
When set to not use the timer input pin, no operating clock is provided to the noise filter circuit.
Therefore, the following wait times are required from the channel operation that is set to use the timer
input pin to the channel operation corresponding to the set timer input pin.
(1) When the noise filter is OFF
If any bit is set in the state that bit12(CCSmn), bit9(STSmn1) and bit8(STSmn0) of the timer mode
register mn (TMRmn) are all 0, it is necessary to set the operation permission trigger of the timer channel
start register (TSm) after at least two running clock (f
MCK
) cycles.
(2) When the noise filter is ON
If any bit is set in the state that bit12(CCSmn), bit9(STSmn1) and bit8(STSmn0) of the timer mode
register mn (TMRmn) are all 0, the operation permission trigger of the timer channel start register (TSm)
must be set at least after four running clock (f
MCK
) cycles.
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