Cmsemicon CMS32L051 - 8-Bit A;D Conversion Result Register (ADCRI); Conversion Result Comparison Upper Limit Setting Register (ADUL); Conversion Result Comparison Lower Limit Setting Register (ADLL)

V1.2.2
CMS32L051 User Manual |Chapter 11 A/D Converter
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11.2.8 8-bit A/D conversion result register (ADCRI)
This is an 8-bit register that holds the results of the A/D conversion, holding a high 8-bit note with 12-bit
resolution.
The ADCRH register is read through an 8-bit memory operation instruction.
After the reset signal is generated, the value of this register becomes 00H.
Note If the value of the A/D conversion result is not in the A/D conversion result comparison function (set via the
ADRCK bit and the ADUL/ADLL register (see Figure 11-8 )) within the set value range, the A/D conversion
results are not saved.
Figure11-11 Format of 8-bit A/D Conversion Result Register (ADCRH)
Reset value: 00H R
7
6
5
4
3
2
1
0
ADCRH
Note The conversion results must be read after the conversion is complete and before configuring the ADM0 and ADS
registers. Otherwise, you may not read the correct conversion results.
11.2.9 Conversion result comparison upper limit setting register (ADUL)
This is the set register used to check the upper limit of the A/D conversion result.
The A/D conversion result is compared to the value of the ADUL register, and the ADRCK in the mode
register 2 (ADM2) of the A/D converter
The set range of bits (see Figure11-7 Range of interrupt signal generation for the ADRCK bit) controls the
generation of the interrupt signal (INTAD). The ADUL register is set via 8-bit memory operation instructions.
After the reset signal is generated, the value of this register changes to FFH.
Note 1 Only the 12-bit A/D is converted to the high 8-bit and ADUL registers of the result register (ADCR) and the ADLL
Registers are compared.
2. To override the ADUL register and the ADLL register, it must be done in the transition stop state (ADCS=0).
3. When setting the ADUL register and the ADLL register, the ADUL must be > ADLL.
Figure11-12 Format of conversion result comparison upper limit setting register (ADUL)
Reset value: FFH R/W
7
6
5
4
3
2
1
0
ADULTS
ADUL7
AOFL6
ADUL5
ADUL4
ADUL3
ADUL2
ADUL1
ADUL0
11.2.10 Conversion result comparison lower limit setting register (ADLL)
This is the set register used to check the lower limit of the A/D conversion result.
The A/D conversion result is compared to the value of the ADLL register, and the ADRCK in the mode
register 2 (ADM2) of the A/D converter
The set range of bits (see FigureFigure11-7 Range of interrupt signal generation for the ADRCK bit)
controls the generation of the interrupt signal (INTAD). The ADLL register is set via an 8-bit memory operation
command.
After the reset signal is generated, the value of this register becomes 00H.