CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.3.3 Timer mode register mn (TMRmn)
The TMRmn register is the register for setting the operation mode of channel n. It carries out the
selection of the operation clock (f
MCK
), the selection of the count clock, the selection of the master/slave,
the selection of the 16-bit/8-bit timer (channel 1 and channel 3 of unit 0 only), the setting of the start trigger
and the capture trigger, the selection of the valid edge of the timer input and the setting of the operation
mode (interval, capture, event counter, single count, capture & single count).
It is forbidden to override the TMRmn register in operation (TEmn=1). However, bit7 and bit6 (CISmn1,
CISmn0) can be overridden in some functions (TEmn=1) (for details, please refer to 5.8 Independent
Channel Operation Function of General Timer Unit and Multi-channel Linkage Operation Function of 5.9
Timer Array Unit).
The TMRmn register is set via a 16-bit memory operation command. After the reset signal is generated, the
value of the TMRmn register changes to 0000H.
Note: Bit11 of the TMRmn register varies from channel to channel.
TMRm2: MASTERmn bit (n=2)
TMRm1, TMRm3: SPLITmn bit (n=1, 3)
TMRm0: fixed as 0.
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