Cmsemicon CMS32L051 - 20.3 Deep sleep mode

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CMS32L051 User Manual |Chapter 20 Standby Function
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20.3 Deep sleep mode
20.3.1 The setting for deep sleep mode
When the SLEEPDEEP bit of the SCR register is 1, the WFI instruction is executed and deep sleep mode
is entered. In this mode, the CPU, most peripheral modules, and the oscillator stop functioning. However, the
values of the CPU's internal registers, RAM data, peripheral modules, and I/O status are maintained. The
operating status of the peripheral module and the oscillator in deep sleep mode is shown in Table 20-2.
Deep sleep mode can only be set if the CPU clock before setting is the primary system clock.
Note When the interrupt mask flag is 0 (allow interrupt processing) and the interrupt request flag is 1 (generates
interrupt request signal), the interrupt request signal is used to release deep sleep mode. Therefore, if the WFI
instruction is executed in this case, it is dismissed as soon as it enters deep sleep mode. Returns to run mode after
executing the WFI instruction and after the deep sleep mode is released.
Table 20-2 Operating status in deep sleep mode
Setting of the deep
sleep mode
Item
Execution of WFI instructions while the CPU is running at the main system clock
CPU runs on a high-speed
internal oscillator clock (F
IH
)
CPU runs on X1 clock (f
X
).
CPU runs on an external
main system clock (F
EX
)
System clock
Stop supplying clocks to the CPU.
Main system
clock
f
IH
Stop it
f
X
f
EX
Subsystem
clock
f
XT
Remains in the state it was in before it was set to deep sleep mode.
f
EXS
f
II
Bit0 (WDSTBYON) and bit4 (WDTON) and the secondary system clock via option bytes
(000C0H) are available
Allows the WUTMMCK0 bit of the mode control register (OSMC) to be set.
WUTMMCK0=1: Oscillation
WUTMMCK0=0 and WDTON=0: Stop
WUTMMCK0=0, WDTON=1 and WDSTBYON=1: Oscillate WUTMMCK0=0, WDTON=1
and WDSTBYON=0: Stop
CPU
Stop running.
Code flash
RAM
Port (latch)
Remains in the state it was in before it was set to deep sleep mode.
Universal timer unit
Disable operation.
Real-time clock (RTC).
Can run.
1 5-bit interval timer
Watchdog timer
See Chapter 10: The Watchdog Timer.
Clock output/buzzer output
Capable of running when the secondary system clock is selected as the count clock
and the RTCLPC bit is 0, otherwise it is disabled.
A/D converter
Can wake up.
Universal Serial
Communication Unit (SCI)
Only SSPIp and UARTq can wake up.
Except for SSPIp and UARTq, it is forbidden to run.
SPI
Disable operation.
Serial Interface (IICA).
Can wake up by address matching.
Data Transfer Controller
(DMA).
Can accept DMA boot sources.
Linkage controller
Links can be made between runnable function blocks.
Power-on reset function
Can run.
Voltage detection function
External interrupts
CRC
operations
function
High-speed
CRC
Stop running.
Generic CRC