CMS32L051 User Manual |Chapter 1 CPU
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Chapter 1 CPU
1.1 Overview
This section briefly introduces the features and debugging features of the ARM Cortex-M0+ core on this
product, please refer to the relevant ARM documentation for details.
1.2 Cortex-M0+ core features
⚫ The ARM Cortex-M0+ processor is a 32-bit RISC core with 2-stage pipeline that only supports
privileged mode
⚫ Single -cycle hardware multiplier
⚫ Nested Vector Interrupt Controller (NVIC)
◼ 1 non-maskable interrupt (NMI)
◼ Supports 32 maskable interrupt requests (IRQs)
◼ 4 interrupt priorities
⚫ System Timer (SysTick) is a 24-bit countdown timer with a choice of f
CLK
or f
IL
counting clock
⚫ Vector Table Offset Register (VTOR)
◼ The software can write VTOR to relocate the vector table start address to a different location
◼ The default value of this register is 0x0000_0000, the low 8 bits are ignored for writes, and
read to zero, which means that the offset is 256 bytes aligned.
1.3 Debugging features
⚫ 2-wire SWD debug interface
⚫ Supports pause, resume, and stepping through programs
⚫ Access the processor's core registers and special function registers
⚫ 4 hardware breakpoints (BPUs).
⚫ Unlimited software breakpoints (BKPT instructions).
⚫ 2 Data observation points (DWTs).
⚫ Memory is accessed while the kernel is executing.
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