Cmsemicon CMS32L051 - Chapter 16 Enhanced DMA; 16.1 The function of DMA

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CMS32L051 User Manual |Chapter 16 Enhanced DMA
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Chapter 16 Enhanced DMA
16.1 The function of DMA
DMA is a function that does not use a CPU and transfers data between memories. Initiate DMA for data
transfer via peripheral function interrupts. When DMA and CPU access the same unit in FLASH, SRAM0,
SRAM1, or peripheral modules at the same time, their bus usage rights are higher than those of the CPU.
When DMA and CPU access different units in FLASH, SRAM0, SRAM1, or peripheral modules, respectively,
the two do not interfere with each other and can be executed in parallel.
The specifications of DMA are shown in Table 16-1.
Table 16-1 DMA specification (1/2)
Item
Specification
Start the source
Up to 24 boot sources
Distributable control data
24 groups
The address
space that
can be
transferred
Address space
Full address range space
source
Full address range space is optional
target
Full address range space is optional
The maximum
number of
transfers
Normal mode
65535 times
Repeating pattern
65535 times
The maximum
transfer block
size
Normal mode
(8-bit transfer).
65535 bytes
Normal mode
(16-bit transmission).
131070 bytes
Normal mode
(32-bit transfer).
262140 bytes
Repeating pattern
65535 bytes
Transmission units
8-bit/16-bit/32-bit
Transfer mode
Normal mode
Ends after transferring the DMACTj register from 1 to 0.
Repeating pattern
At the end of the transfer of the DMACTj register from 1 to 0, the
address of the duplicate area is initialized before the DMRLDj is placed
The value of the register is reloaded into the DMACTj register and then
transferred.
Address control
Normal mode
Fixed or incremental
Repeating pattern
Fixed or incremented distinct addresses.
The priority of the startup source
Refer to Table 16-5 DMA startup source and vector address