CMS32L051 User Manual |Chapter 16 Enhanced DMA
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Table 16-1 DMA specification (2/2)
When transferring the DMACTj register from 1 to 0, an interrupt from the startup
source is requested to the CPU and interrupt handling is performed.
The RPTINT bit of the DMACRj register is 1 to allow interrupts to be generated) and the
DMACTj register is transferred from 1 to 0 when the data transfer is made The CPU
requests an interrupt from the start source and performs interrupt handling.
If the DMAENi0~DMAENi7 bits of the DMAENi register is "1" (boot allowed), the
transmission of data begins each time the DMA boot source occurs.
Set DMAENi0~DMAENi7 bits to "0" (boot is prohibited).
the DMACTj register changes from 1 to 0 at the end of the data transfer
Set DMAENi0~DMAENi7 bits to "0" (boot is prohibited).
RPTINT bit is 1 (allows interrupts to occur) and the DMACTj register
changes from 1 to 0 at the end of the data transfer
Note In deep sleep mode because the flash memory stops functioning and therefore cannot be used as a DMA transfer
source.
Note i=0~2, j=0~23
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