Cmsemicon CMS32L051 - Timer Output Level Register M (Tolm)

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CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.3.11 Timer output level register m (TOLm)
The TOLm register is a register that controls the output level of each channel timer.
When the timer output (TOEmn=1) is enabled and the multichannel linkage operation function
(TOMmn=1) is used, the timing of the set and reset of the timer output signal reflects the inverting setting
of each channel n made by this register. In the main channel output mode (TOMmn=0), the setting of this
register is invalid.
The TOLm register is set via a 16-bit memory operation instruction.
The lower 8 bits of the TOLm register can be set with TOLmL and via 8-bit memory operation
instructions. After the reset signal is generated, the value of the TOLm register changes to 0000H.
Figure 5-20 Table of timer output level register m (TOLm)
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOLm
TOLmn
Control of the timer output level of channel n
0
Positive logic output (active high-level)
1
Inverting output (active low-level)
Note: bit15 to 4 and bit0 must be set to 0.
Remark 1: If you override the value of this register while the timer is running, the output logic of the timer is reversed the
next time the timer output signal changes, rather than immediately after the override.
2. m: unit number (m=0,1) n: channel number (n=0~3).
0
0
0
0
0
0
0
0
0
0
0
0
TOL
m3
TOL
m2
TOL
m1
0