CMS32L051 User Manual |Chapter 11 A/D Converter
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11.4.11 Hardware trigger wait mode (scan mode, continuous conversion mode)
(1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is 1 into a
hardware-triggered standby state.
(2) If hardware triggers are entered in hardware-triggered standby, A/D conversion is performed on the
four analog input channels specified by the analog input channel specified registers (ADS) from scan
0 to scan 3. The ADCS bit of the ADM0 register is automatically 1 while the input hardware triggers.
A/D conversion is performed sequentially from the analog input channels specified by Scan 0.
(3) A/D conversion of 4 analog input channels in succession. Whenever the A/D conversion ends, the
conversion results are saved to the A/D conversion result register (ADCR, ADCRH) and an A/D
conversion end interrupt request signal is generated (INTAD). Immediately after the A/D conversion
of the 4 channels is completed, the next A/D conversion is automatically started from the set channel.
(4) If the input hardware triggers during the conversion, the current A/D conversion is aborted
immediately and then restarted from the original channel.
(5) If the ADS registers are overwritten or overwritten during the conversion, the current A/D conversion
is aborted immediately and the scan conversion begins with the channel respecified by the ADS
registers.
(6) If you override the ADCS bit 1 during the conversion process, the current A/D conversion is aborted
immediately and the conversion is restarted from the original channel.
(7) If the ADCS bit is 0 during the transition, the current A/D transition is aborted immediately, then
enters a hardware-triggered standby state, and the A/D converter enters a stopped state. When the
ADCE bit is 0, even the input hardware trigger is ignored and the A/D conversion does not begin.
Figure11-26 Timing example of hardware trigger wait mode (scan mode, continuous conversion mode)
power
source
A/D conversion state
stop
converting
idle
conversion
start next cnversion
when A/D conversion
completes
auto restart
conversion when
conversion completes
auto restart
conversion when
conversion completes
auto restart
conversion when
conversion completes
idle
conversion
stop
converting
set 1 to ADCE bit
generate hardware trigger
hardware trigger
do not accept trigger
trigger idle
generate hardware trigger
during A/D conversion
operation
clear ADCE bit to 0
do not accept trigger
modify ADS (from ANI0 to ANI4)
during A/D conversion
clear ADCS bit to 0
during conversion
rewrite ADCS bit to 1
during A/D conversion
operation
trigger idle
4 interrupts generated in 1 complete scan 4 interrupts generated in 1 complete scan
4 interrupts generated in 1 complete scan 4 interrupts generated in 1 complete scan
power source
power source stablization wait cycles
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