Cmsemicon CMS32L051 - DMA Block Size Register J (Dmblsj) (J=0~23)

V1.2.2
CMS32L051 User Manual |Chapter 16 Enhanced DMA
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16.3.6 DMA block size register j (DMBLSj) (j=0~23)
This register sets the block size of the 1 initiation transfer of data.
Figure 16-7of DMA block size register j (DMBLSj).
Address:
Refer to 16.3.2
Control data allocation
.
After reset: Indefinite value
R/W
Symbol:
15
14
13
12
11
10
9
8
DMBLSj
DMBLSj15
DMBLSj14
DMBLSj13
DMBLSj12
DMBLSj11
DMBLSj10
DMBLSj9
DMBLSj8
7
6
5
4
3
2
1
0
DMBLSj7
DMBLSj6
DMBLSj5
DMBLSj4
DMBLSj3
DMBLSj2
DMBLSj1
DMBLSj0
DMBLSj
The transfer block size
8-bit transfer
16-bit transfer
32-bit transfer
00H
Disable the setting
Disable the setting
Disable the setting
01H
1 byte
2 bytes
4 bytes
02H
2 bytes
4 bytes
8 bytes
03H
3 bytes
6 bytes
12 bytes












FDH
253 bytes
506 bytes
1012 bytes
FEH
254 bytes
508 bytes
1016 bytes
FFH
255 bytes
510 bytes
1020 bytes












FFFFH
65535 bytes
131070 bytes
262140 bytes
Note 1. DMBLSj register cannot be accessed via DMA transfer.