EasyManua.ls Logo

Cmsemicon CMS32L051 - Peripheral Enable Register 0 (PER0)

Default Icon
703 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
V1.2.2
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
www.mcu.com.cn 120 / 703
5.3.1 Peripheral enable register 0 (PER0)
The PER0 register is a register that sets the clock to be enabled or disenabled to be supplied to
each peripheral hardware. Reduce power consumption and noise by stopping clocking unused
hardware.
To use universal timer unit 0, bit0 (TM40EN) must be set to 1. The PER0 register is set via an 8-bit
memory operation command. After the reset signal is generated, the value of the PER0 register changes to
00H.
Figure 5-6 Table of peripheral enable register 0 (PER0).
Address: 0x40020420
After reset: 00H
R/W
symbol
7
6
5
4
3
2
1
0
PER0
RTCEN
IRDAEN
ADCEN
IICA0EN
SAU1EN
SAU0EN
TM41EN
TM40EN
TM40EN
Control of the input clock of the universal timer unit 0
0
Stop supplying the input clock.
the SFR used by General Timer Unit 0.
 0 is in the reset state.
1
An input clock is provided.
 used in general-purpose timer unit 0.
TM41IN
Control of the input clock of the universal timer unit 1
0
Stop supplying the input clock.
 used by universal timer unit 1.
 1 is in a reset state.
1
An input clock is provided.

Note 1 To set the general-purpose timer unit, the following registers must first be set in the TM4mEN bit 1. When the
TM4mEN bit is 0, the value of the control register of the timer array unit is the initial value, ignoring the write
operation (timer input and output selection register 0 (TIOS0), noise filter enable register 1 (NFEN1), noise filter
enable register 2 (NFEN2), port mode control register PMCx, Port mode register PMx and port multiplexing function
configuration register PxxCFG).
atus register mn (TSRmn).
 m (TEm).
 m (TSm).
 m (TTm).
 m (TOEm).
 m (TOm).
 m (TOLm).
 m (TOMm).

Table of Contents

Related product manuals