Cmsemicon CMS32L051 - Interrupt Mask Flag Register (MK00~MK31)

V1.2.2
CMS32L051 User Manual |Chapter 18 Interrupt Function
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18.3.2 Interrupt mask flag register (MK00~MK31)
The interrupt masking flag setting allows or disables the corresponding maskable interrupt processing.
Set the MK00L~MK31L registers via 8-bit memory operation instructions or set MK00~MK31 registers via
32-bit memory operation instructions.
After the reset signal is generated, the values of these registers become FFFF_FFFF.
Figure 18-3 Format of interrupt request masking register (MKm) (m=0~31)
address:MK00:40006100H,MK01:40006104H,MK02:40006108H,MK03:4000610CH
MK04:40006110H,MK05:40006114H,MK06:40006118H,MK07:4000611CH
MK08:40006120H,MK09:40006124H,MK10:40006128H,MK11:4000612CH
MK12:40006130H,MK13:40006134H,MK14:40006138H,MK15:4000613CH
MK16:40006140H,MK17:40006144H,MK18:40006148H,MK19:4000614CH
MK20:40006150H,MK21:40006154H,MK22:40006158H,MK23:4000615CH
MK24:40006160H,MK25:40006164H,MK26:40006168H,MK27:4000616CH
MK28:40006170H,MK29:40006174H,MK30:40006178H,MK31:4000617CH
Reset value: FFFF_FFFFHR/W
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
MKmL
Reserved
MKL
MKmL
Interrupt handling control for interrupt sources
numbered 0 to 31Note 1
0
Interrupt handling is allowed.
1
Interrupt processing is prohibited.
Note: 1. The correspondence between the interrupt source and the interrupt request masking register is
shown in Table 18-2
2. The correspondence between the interrupt request flag register and CPU.IRQ is shown in Figure
18-4