Cmsemicon CMS32L051 - Port Clear Control Register (Pclrxx)

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CMS32L051 User Manual |Chapter 2 Pin Function
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2.3.4 Port clear control register (PCLRxx)
This is the register to set the port output latch in bit units. After a reset signal is generated, the value of
the register becomes 00H.
Register address = base address + offset address; the base address of the port Clearance control
register is 0x40040000, and the offset address is shown in the following figure.
Figure 2-4 Format of port clear control register
symbol
7
6
5
4
3
2
1
0
address
after reset
R/W
PCLR0
0
0
0
0
0
0
PCLR01
PCLR00
0x070
00H
W
PCLR1
PCLR17
PCLR16
PCLR15
PCLR14
PCLR13
PCLR12
PCLR11
PCLR10
0x071
00H
W
PCLR2
PCLR27
PCLR26
PCLR25
PCLR24
PCLR23
PCLR22
PCLR21
PCLR20
0x072
00H
W
PCLR3
0
0
0
0
0
0
PCLR31
PCLR30
0x073
00H
W
PCLR4
0
0
0
0
0
0
PCLR41
PCLR40
0x074
00H
W
PCLR5
0
0
0
0
0
0
PCLR51
PCLR50
0x075
00H
W
PCLR6
0
0
0
0
PCLR63
PCLR62
PCLR61
PCLR60
0x076
00H
W
PCLR7
0
0
PCLR75
PCLR74
PCLR73
PCLR72
PCLR71
PCLR70
0x077
00H
W
PCLR12
0
0
0
PCLR124
PCLR123
PCLR122
PCLR121
PCLR120
0x07C
00H
W
PCLR13
PCLR137
PCLR136
0
0
0
0
0
PCLR130
0x07D
00H
W
PCLR14
PCLR147
PCLR146
0
0
0
0
0
PCLR140
0x07E
00H
W
PCLRmn
Clear control of the Pmn pin (m=0~7, 12~14, n=0~7).
0
No action
1
Clear the corresponding Pmn
Note 1. The initial value must be set for the unassigned bits.