Cmsemicon CMS32L051 - Hardware Trigger Wait Mode (Select Mode, Continuous Conversion Mode)

V1.2.2
CMS32L051 User Manual |Chapter 11 A/D Converter
www.mcu.com.cn 291 / 703
11.4.9 Hardware trigger wait mode (select mode, continuous conversion mode)
(1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is 1 into a
hardware-triggered standby state.
(2) If hardware triggers are entered in hardware-triggered standby, the analog inputs specified by the
analog input channel specified registers (ADS) are A/D converted. The ADCS bit of the ADM0
register is automatically 1 while the input hardware triggers.
(3) If the A/D conversion ends, the conversion results are saved to the A/D conversion result register
(ADCR, ADCRH) and an A/D conversion end interrupt request signal (INTAD) is generated). Start the
next A/D conversion immediately after the A/D conversion is over (at this point, no hardware
triggering is required).
(4) If the input hardware triggers during the conversion, the current A/D conversion is aborted
immediately and then restarted.
(5) If the ADS registers are overwritten or overwritten during the conversion, the current A/D conversion
is aborted immediately, and then the analog input respecified by the ADS register is A/D converted.
(6) If you override the 1 to the ADCS bit during the conversion, the current A/D conversion is aborted
immediately and the conversion begins again.
(7) If the ADCS bit is 0 during the transition, the current A/D transition is aborted immediately, then
enters a hardware-triggered standby state, and the A/D converter enters a stopped state. When the
ADCE bit is 0, even the input hardware trigger is ignored and the A/D conversion does not begin.
Figure11-24 Timing example of hardware trigger wait mode (select mode, continuous conversion mode)
set 1 to ADCE bit
generate hardware trigger
hardware trigger
do not accept trigger trigger idle
generate hardware
trigger during A/D
conversion operation
clear ADCE bit to 0
do not accept trigger
modify ADS (from ANI0 to ANI1) during
A/D conversion
clear ADCS bit to 0 during
conversion
rewrite ADCS bit to 1 during A/
D conversion operation
trigger idle
start next cnversion
when A/D conversion
completes
auto restart
conversion when
conversion completes
auto restart
conversion when
conversion
completes


auto restart
conversion when
conversion
completes

stop
converting
idle
conversion
A/D conversion state
stop
converting
idle
conversion
power
source
power source
power source stablization wait cycles