CMS32L051 User Manual |Chapter 20 Standby Function
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20.2.2 Release of sleep mode
Sleep mode can be interrupted with any interrupt as well as an external reset terminal, POR reset, low
voltage sense reset, RAM parity error reset, WDT reset, and software reset to be released.
(1) Release by interrupting
When an unmasked interrupt is generated and it is in a state that allows interrupts to be accepted, sleep
mode is released and the CPU begins processing the interrupt service program.
Figure 20-1 Release sleep mode by interrupting requests
standby release signal
CPU status normal operation
Note2
release sleep mode, execute next instruction
note1
sleep mode
Note 1. From the standby dismissal signal generation to the sleep mode dismissal, it takes 16 clocks to start
the interrupt service program.
2. The standby release signal cannot be cleared by itself, and the register must be cleared. Register
clearing is usually written in an interrupt service program.
Note: Before entering sleep mode, only the mask bit that is expected to be used to release the
interrupt in sleep mode should be cleared.
(2) Release by reset
When a reset signal is generated, the CPU is reset and sleep mode is released. As with the usual reset, the
program is executed after transfer to the reset vector address.
Figure 20-2 Release sleep mode by reset
CPU status normal operation
sleep mode
reset signal
reset period
reset process
note1
normal operation
Note 1: For reset processing, please refer to Chapter 21 Reset Function. For the reset of power-
on reset (POR) circuits and voltage detection (LVD) circuits, refer to Chapter 2, Power-On Reset
Circuits.
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