CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit
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23.4.3 Settings for interrupt & reset mode
The operating mode (interrupt & reset mode (LVIMDS1, LVIMDS0=1, 0)) and the sense voltage (V
LVDH
,
VLVDL) are set by option byte 000C1H).
If the interrupt & reset mode is set, it starts operating in the following initialization state.
(LVISEN) of the voltage sense register (LVIM) to 0 (disable overriding of the voltage sense
register (LVIS)).
voltage sense level register (LVIS) to 00H. bit7 (LVIMD) is 0 (interrupt
mode).
Bit0 (LVILV) is 0 (high voltage sense level: V
LVDH
).
Operation of LVD interrupt & reset mode
When power is turned on, the interrupt & reset mode (LVIMDS1, LVIMDS0 = 1, 0 of the option byte)
maintains the internal reset state of LVD until the power supply voltage (V
DD
) exceeds the high voltage detect
level (V
LVDH
). If the supply voltage (V
DD
) exceeds the high voltage detection level (V
LVDH
), the internal reset is
released.
When the operating voltage drops, if the supply voltage (V
DD
) is below the high voltage detection level
(V
LVDH
), an interrupt request signal (INTLVI) is generated for the LVD and any stack processing can be
performed. After that, if the supply voltage (V
DD
) is lower than the low voltage detection level (V
LVDL
), an internal
reset of LVD is generated. However, after INTLVI occurs, the interrupt request signal is not generated even if
the supply voltage (V
DD
) returns to the high voltage detection voltage (V
LVDH
) or higher without falling below the
low voltage detection voltage (V
LVDL
).
When using the LVD interrupt & reset mode, you must follow the steps in the flowchart shown in "Figure
23-7 Setup steps for confirmation/reset of the operating voltage " and "Figure 23-8 Initial Setting Procedure
for Interrupt & Reset Mode".
The internal reset signal and the generation timing of the interrupt signal in the LVD interrupt & reset
mode are Figure 23-6.
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