CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
www.mcu.com.cn 197 / 703
5.9.3 Operates as multiplex PWM output function
This is the ability to perform multiple PWM outputs by extending the PWM functionality and using multiple
slave channels for different duty cycles. For example, when 2 slave channels are used in pairs, the period and
duty cycle of the output pulse can be calculated using the following formula:
Note When the set value of TDRmp (slave 1) > {setting value of TDRmn (master) +1} or {setting value of TDRmq (slave 2)} >
{setting value of TDRmn (master) +1}, the duty cycle exceeds 100%, but is 100% output.
In interval timer mode, the timer count register mn (TCRmn) of the master channel runs and counts
cycles. In single-count mode, the TCRmp register of slave channel 1 runs and counts the duty cycle and
outputs the PWM waveform from the TOmp pin. Starting with the INTTMmn of the master channel, the value
of the timer data register mp (TDRmp) is loaded into the TCRmp register and decremented in the count. If
TCRmp becomes 0000H, INTTMmp is output and counts are stopped before the next start trigger (INTTMmn
of the master channel) is entered. After the INTTMmn is generated from the master channel and 1 count clock
has passed, the output level of TOmp becomes effective if TCRmp becomes 0000H, it becomes an invalid
level.
As with the TCRmp register of slave channel 1, in single-count mode, the TCRmq register of slave channel
2 runs and counts the duty cycle and outputs the PWM from the TOmq pin waveform. Starting with the INTTMmn
of the master channel, the value of the TDRmq register is loaded into the TCRmq register and decremented in
the count. If TCRmq becomes 0000H, INTTMmq is output and counts are stopped before the next start trigger
(INTTMmn of the master channel) is entered. After the INTTMmn is generated from the master channel and 1
count clock has passed, the output level of TOmq becomes effective if the TCRmq becomes 0000H, it becomes
an invalid level.
When channel 0 is used as the master channel in this operation, up to 3 PWM signals can be output
simultaneously.
Note To overwrite the timer data register mn (TDRmn) of the master channel and the TDRmp register of slave channel 1 at
the same time, at least 2 write accesses are required. Because the values of the TDRmn register and TDRmp register are loaded
into the TCRmn register and the TCRmp register when the INTTMmn is generated on the master channel, Therefore, if the
INTTMmn is rewritten before and after the intake is generated on the master channel, the TOmp pin cannot output the expected
waveform. Therefore, to override both the TDRmn registers of the master and the TDRmp registers of the slave, the 2 registers
must be overwritten immediately after the INTTMmn is generated on the master channel (the same applies to the slave channels).
TDRmq register of 2).
Note m: Unit number (m= 0,1) n: Master channel number (n=0).
p: slave channel number q: slave channel number
n＜p＜(p and q are integer greater than n)
To Next Page
Loading...