Cmsemicon CMS32L051 - Page 198

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CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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Figure 5-73 Block diagram of operation as multiple PWM output function (when outputting 2 kinds of PWM)
(interval Timer mode)
master control channel
operational clock
operational clock
operational clock
(single counting mode)
slave channel2
(single counting mode)
slave channel1
clock
selection
trigger
selection
clock
selection
trigger
selection
clock
selection
trigger
selection
Timer count register
mn (TCRmn)
Timer data register
mn (TDRmn)
Timer count register
mp (TCRmp)
Timer data register
mp (TDRmp)
interrupt
control
circuit
output
control
circuit
interrupt
control
circuit
TOmp Pin
interrupt signal
(INTTMmn)
interrupt signal
(INTTMmp)
Timer count register
mq (TCRmq)
Timer data register
mq (TDRmq)
output
control
circuit
interrupt
control
circuit
TOmq Pin
interrupt signal
(INTTMmq)
Remark m: Unit number (m= 0,1) n: master channel number (n=0).
p: slave channel number q: slave channel number
n＜p＜(p and q are integers greater than n)