CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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4.3 Registers for controlling clock generation circuit
The clock generation circuit is controlled by the following registers.
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Clock operation mode control register (CMC)
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System clock control registers (CKC)
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Clock operation status control register (CSC)
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Status register of the oscillation stabilization time counter (OSTC)
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Oscillation stabilization time selection register (OSTS)
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Peripheral enable registers 0, 1 (PER 0, PER1)
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Subsystem clock supply mode control register (OSMC)
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High-speed internal oscillator frequency selection register (HOCODIV)
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High-speed internal oscillator trim register (HIOTRM)
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Subsystem clock selection register (SUBCKSEL)
Note: Assigned registers and bits vary from product to product. You must set an initial value for unassigned bits.
4.3.1 Clock operation mode control register (CMC).
This is the register that sets the operating mode of the X1/P 121, X2/EXCLK/P 122, XT1/P123,
XT2/EXCLKS/P1 24 pins and selects the oscillation circuit gain.
After the reset is released, the CMC register can only be written once via the 8-bit memory operation
command. This register can be read via 8-bit memory operation instructions.
After the reset signal is generated, the value of this register becomes 00H.
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