CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.9.4 Generation of stop condition
After all data is sent and received with the object slave, a stop condition is created and the bus is
released.
(1) Process flow
Figure 12-128 Timing diagram for generating stop condition
STmn
SEmn
SOEmn
note
SCLr output
SDAr
output
stop
operating
SOmn
bit operation
CKOmn
bit operation
SOmn
bit operation
stop condition
Note The SOEmn bit of the serial output allow register m (SOEm) is set to "0" before the last data is received.
Figure 12-129 Flow chart of generating a stop condition
stop condition generation starts
Write 1 to
STmn bit (SEmn=0)
Write 0 to SOEmn bit
Write 0 to SOmn bit
Write 1 to CKOmn bit
wait
Write 1 to SOmn bit
IIC communication completes.
operation stop state (can operate
CKOmn bit)
to compliant to I
2
C bus standard,
ensure wait time.
data transmission completes/data
reception completes.
output disable state (can operate
SOmn bit)
timing sequence must compliant
to I
2
C bus SCL low voltage width
standard.
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