CMS32L051 User Manual |Chapter 14 Serial interface IICA
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(4) Release method of the wait
There are 4 ways to undo the waiting:
IICA shift register n (IICAn).
Set bit5 (WRELn) of IICA control register n0 (IICCTLn0) (unwait).
Set bit1 (STTn) of the IICCTLn0 register (generate start condition)
Note
.
Set bit0 (SPTn) of the IICCTLn0 register (generate stop condition)
Note
.
Note: Only for the master control device.
When selecting a wait for 8 clocks (WTIMn=0), you need to decide whether to generate a reply before
release wait.
(5) Detection of stop conditions
If a stop condition is detected, INTIICAn is generated (only in the case of SPIEn=1).
14.5.9 Detection method for address matching
In I
2
C-bus mode, the master device can select a specific slave by sending a slave address. Address
matching can be automatically detected by hardware. An INTIICAn interrupt request is generated when the
slave address sent by the master device and the set address of the slave address register n (SVAn) are the
same or only the extension code is received.
14.5.10 Detection of errors
In I
2
C-bus mode, because the state of the serial data bus (SDAAn) during the transmit is fetched to the IICA
shift register n (IICAn) of the transmitting device, Therefore, I can detect sending errors by comparing the IICA
data before and after the start of the transmission. In this case, if the two data are different, it is judged that a
sending error has occurred.
Remark n=0
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