Cmsemicon CMS32L051 - A;D Converter Mode Register 1 (ADM1)

V1.2.2
CMS32L051 User Manual |Chapter 11 A/D Converter
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11.2.3 A/D converter mode register 1 (ADM1)
This is the register that sets the A/D conversion mode.
The ADM1 register is set via 8-bit memory operation instructions.
After the reset signal is generated, the value of this register becomes 00H.
Figure11-5 Format of A/D converter mode register 1 (ADM1)
Reset value: 00H
R/W
7
6
5
4
3
2
1
0
ADM1
ADMD
0
0
0
ADSCM
0
0
0
ADMD
Setting of the A/D conversion channel selection mode
0
Select mode
1
Scan mode
ADSCM
Setting of the A/D conversion mode
0
Continuous conversion mode
1
Single conversion mode
Note: You must set bit6~4,2 to 0.
Note 1. To override the ADM1 register, it must be done in the transition stop state (ADCS=0).
2. In order to end the A/D conversion normally, the hardware trigger interval must be set at least to the following time:
When hardware triggers no-wait mode: 2 f-CLK clocks + A/D conversion time
When the hardware triggers the wait mode: 2 fCLK clock + A/D power supply stable wait time + A/D transition time
Note 1. f
CLK
: Clock frequency of the CPU/peripheral hardware