Cmsemicon CMS32L051 - 16.3 Registers for controlling DMA

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CMS32L051 User Manual |Chapter 16 Enhanced DMA
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16.3 Registers for controlling DMA
The registers that control the DMA are shown in Table 16-2.
Table 16-2 Registers for controlling DMA
Register Name
Symbol
Peripheral enable register 1
PER1
DMA boot enable register 0
DMAEN0
DMA boot enable register 1
DMAEN1
DMA boot enable register 2
DMAEN2
DMA base address register
DMABAR
The control data of the DMA is shown in Table 16-3.
The DMA control data is distributed in the DMA control data area of the RAM. The DMA control data
area and the 416-byte region containing the DMA vector table area (the starting address where the control
data is saved) are set via the DMABAR register.
Table 16-3 Control data for DMA
Register name
Symbol
DMA control register j
DMACRj
DMA block size register j
DMBLSj
DMA transfer count register j
DMACTj
DMA transfer number of times to reload register j
DMRLDj
DMA source address register j
DMSARj
DMA destination address register j
DMDARj
Note j=0~23