CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.9.2 Operates as PWM function
Using 2 channels in pairs, pulses of any period and duty cycle can be generated. The period and
duty cycle of the output pulse can be calculated using the following calculation formula:
Note When the config value of TDRmp (slave) > the config value of {TDRmn (master) +1}, the duty cycle exceeds 100%, but it
is 100% output.
The master channel is used as an interval timer mode. If the channel starts triggerring bit (TSmn) of the
timer channel start register m (TSm) is set to 1, the output interrupt (INTTMmn) is then loaded into the timer
count register mn by the config value of the timer data register mn (TDRmn), and the count is decremented by
counting the clock. When counted to 0000H, the value of the TDRmn register is loaded into the TCRmn
register again after the INTTMmn is output, and the count is decremented. Thereafter, repeat this operation
before setting the channel stop touch bit (TTmn) of the timer channel stop register m (TTm) to 1.
When used as a PWM function, the master channel is decremented in count for PWM output (TOmp)
cycles during the period counted to 0000H. The slave channel is used as a single-count mode. Starting with
the INTTMmn of the master channel, the value of the TDRmp register is loaded into the TCRmp register and
decremented counting until 0000H. When counted to 0000H, INTTMmp is output and waits for the next ON
Initial trigger (INTTMmn for the master channel).
When used as a PWM function, the slave channel is decremented and counted as the duty cycle of the
PWM output (TOmp) for the period counted to 0000H.
After generating INTTMmn from the master channel and passing 1 clock, the PWM output (TOmp)
becomes effective and the value of the TCRmp register on the slave channel is 0000H becomes an invalid
level.
Notice: Two write accesses are required to overwrite both the timer data register mn (TDRmn) of the master channel and
the TDRmp register of the slave channel. Because the values of the TDRmn register and TDRmp register are
loaded into the TCRmn register and the TCRmp register when the master channel generates INTTMmn. In this
case, if INTTMmn is rewritten before and after the main channel is generated, the TOmp pin cannot output the
expected waveform. Therefore, to overwrite both the TDRmn registers of the master and the TDRmp registers of
the slave, the two registers must be overwritten immediately after the INTTMmn is generated on the master
channel.
Note m: Unit number (m= 0,1) n: master channel number (n=0, 2) p: slave channel number (n= 0: p=1, 2, 3, n=2: p=3)
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