CMS32L051 User Manual |Chapter 16 Enhanced DMA
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16.5.4 Response time of DMA
The DMA response time is shown in Table 16-12. DMA response time refers to the time from the time the
DMA boot source is detected to the start of the DMA transfer, excluding the number of execution clocks for the
DMA.
Table 16-12 Response time for DMA
However, the response of the DMA may also be delayed in the following cases. The number of clocks
delayed varies depending on the condition.
Maximum response time for the execution of instructions from internal RAM: 20 clocks
Note 1 clock: 1/f CLK (fCLK: CPU/peripheral hardware clock).
16.5.5 Startup source for DMA
You cannot enter the same startup source between entering the DMA startup source and ending the
DMA transfer.
At the location where the DMA boot source is generated, the DMA boot allow bit corresponding to that
boot source cannot be manipulated.
If the DMA boot source sends a race, the priority is determined when the CPU accepts the DMA
transmission and determines the boot source. For priority of startup sources, refer to the 16.3.3 Vector table.
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