Cmsemicon CMS32L051 - Serial Data Register Mn (Sdrmn)

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
www.mcu.com.cn 311 / 703
12.3.5 Serial data register mn (SDRmn).
The SDRmn register is the data register (16 bits) that channel n transmits and receives.
The bits 8 to 0 (low 9 bits) of SDR00 and SDR01 or bits 7 to 0 (low 8 bits) of SDR02, SDR03, SDR10 and
SDR11 are used as transmit and receive buffer registers, and bits 15 to 9 (high 7 bits) are used as operating
clock (f
MCK
) divider setting registers.
If the CCSmn bit of the serial mode register mn (SMRmn) is set to "0", the divider clock of the operation
clock set by bits 15 to 9 (high 7 bits) of the SDRmn register is used as the transmit clock.
If the CCSmn bit is set to "1", bit15~9 (high 7 bits) of SDRmn must be set to 0000000B. The input clock
f
SCLK
(slave transfer in SSPI mode) of the SCLKp pin is the transmit clock.
The low 8 or 9 bits of the SDRmn register are used as transmit and receive buffer registers. When
receiving data, shift registers are converted in parallel data is saved to the lowest 8 bits or the lower 9 bits;
When transmitting data, the transmitted data to the shift register is set to a lower 8 bits or a low 9 bits.
SDRmn registers can be read and written in 16-bit increments. However, high 7 bits can only be read and
written when the operation is stopped (SEmn=0). In operation (SEmn=1) only the low 8 bits or 9 bits of the
SDRmn register can be written, and the high 7 bits of the SDRmn register are always read as "0".
After the reset signal is generated, the value of the SDRmn register changes to 0000H.
Figure 12-9 Format of serial data register mn (SDRmn)
Address: 40041310 H (SDR00), 40041312H (SDR01) After reset: 0000HR/W
40041748H(SDR10), 4004174AH(SDR11)
40041211H (in the case of SDR00) 40041310H (in the case of SDR00).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
Address: 4004134 4H (SDR02), 40041346H (SDR03) after reset: 0000HR/W
40041345H (in the case of SDR02) 40041344H (in the case of SDR02).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SDRmn
0
SDRmn[15:9]
Run the transmit clock setting for clock division
0
0
0
0
0
0
0
f
MCK
/2
0
0
0
0
0
0
1
f
MCK
/4
0
0
0
0
0
1
0
f
MCK
/6
0
0
0
0
0
1
1
f
MCK
/8
























1
1
1
1
1
1
0
f
MCK
/254
1
1
1
1
1
1
1
f
MCK
/256
Note 1. Bit8 of the SDR02, SDR03, SDR10, and SDR11 registers must be set to 0.
2. When using UART, it is forbidden to set SDRmn [15:9] to 0000000B and 0000001B.
3. When using Simplified I2C, it is forbidden to set SDRmn[15:9] to 0000000B, and the SDRmn [15:9] setting value must