Cmsemicon CMS32L051 - 23.5 Considerations for voltage detection circuits

V1.2.2
CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit
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23.5 Considerations for voltage detection circuits
(1) Regarding voltage fluctuations when the power is turned on
For systems where the supply voltage (V
DD
) fluctuates for a certain amount of time near the LVD
sense voltage, it is possible to repeatedly enter the reset state and the reset release state. The following
processing can be used to set the time of release reset to the start of the microcontroller operation
arbitrarily.
< processing > after the reset is released, the initial setting of the port, etc. must be made by using
the software counter of the timer and waiting for different supply voltage fluctuation times for each
system.
Figure 23-9 Example of software processing when the supply voltage fluctuation near the LVD detection
voltage does not exceed 50ms
reset
initialization
after 50ms?
configure TIMER4
(measure 50ms)
clear WDT
Yes
No
refer to diagram 28-5 reset source
confirmation steps
example fCLK=high speed internal osc
clock(4.04Mhz(MAX))
source：fMCK = (4.04MHz(MAX.))/28,
assuming compared value = 789，approximately 50ms
port initial configuration
configure system clock frequency division, timer,
A/D convertoretc
initialization
Note
Note If a reset occurs again during this period, it is not transferred to initialization processing (2).