CMS32L051 User Manual |Chapter 23 Voltage Detection Circuit
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If the interrupt & reset mode is set (LVIMDS1, LVIMDS0=1, 0), it is required after the LVD reset
(LVIRF=1) is released. Voltage detection settling wait time of 400us or 5 f-IL clocks. The LVIMD bit clear
0 must be initialized after waiting for the voltage detection to stabilize. During the counting of the voltage
detection stabilization wait time and when overwriting the LVIMD bit, the LVISEN position 1 must be
used to mask the reset or interrupt generation caused by the LVD.
The initial setup steps for the interrupt & reset mode are shown in Figure 23-8.
Figure 23-8 Initial setup steps for interrupt & reset mode
power supply voltage arise
confirm reset source
LVIRF= 1？
LVISEN = 1
wait time of voltage detection
stablization
Yes
No
refer to diagram 28-5 reset source
confirmation steps
set LVISEN bit to "1",mask voltage
detection(LVIOMSK=1).
set LVIMD bit to "0", configure
interrupt mode
confirm LVD circuit generates internal reset
LVIMD = 0
LVISEN = 0
normal operation
set LVISEN bit to "0", enable
voltage detection
perform 400us or 5 fIL clock cycle counting
via software
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