Cmsemicon CMS32L051 - Clock Error Correction Register (SUBCUD)

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CMS32L051 User Manual |Chapter 7 Real-Time Clock
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7.3.5 Clock error correction register (SUBCUD)
This is a register that can correct clock speed with high accuracy by changing the overflow value
(reference value: 7FFFH) from the internal counter (16 bits) to the second count register (SEC).
The SUBCUD register is set via a 16-bit memory operation command. After the reset signal is
generated, the value of this register becomes 00 00H.
Figure 7-6 Format of clock error correction register (SUBCUD)
Address: 0x40044F34H After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9 8
SUBCUD
7 6 5 4 3 2 1 0
F7
F6
F5
F4
F3
F2
F1
F0
DEV
Timing setting for correction of clock errors
0
Correction of clock error is performed when the seconds are 00, 20, 40 (every 20
seconds).
1
Correction of clock error is performed only when the second bit is 00 (every 60 seconds).
Writing of the SUBCUD register is prohibited during the following period:
, 20H, 40H period
 SEC=00H period
F12
Setting of clock error correction value
0
{(F11,F10,F9,F8,F7,F6,F5,F4,F3,F2,F1,F0)1} ×2 added
1
{(/F11,/F10,/F9,/F8,/F7,/F6,/F5,/F4,/F3,/F2,/F1,/F0)+1} ×2 reduced
When (F12, F11, F10, F9, F8, F7, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) or ( 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1),
no correction of clock error is performed.
Range of correction values: (F12=0)2, 4, 6, 8, ... , 8186, 8188
(F12=1)2, 4, 6, 8, , 8186, 8188
Note: The / indicates the value after the inverse of each bit.
The range of corrections that can be made by clock error correction registers (SUBCUDs) is shown
below.
DEV = 0 (correction every 20 seconds)
DEV = 1 (correction every 60 seconds)
Correctable range
-12496.9ppm~12496.9ppm
-4165.6ppmto4165.6ppm
Max. quantization error
±1.53ppm
±0.51ppm
Min. resolution
±3.05ppm
±1.02ppm
Note When the correction range is outside the range of 4165.6ppm to 4165.6ppm, the DEV bit must be 0.
THEV
0
0
F12
F11
F10
F9
F8