Cmsemicon CMS32L051 - Simple I 2 C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.1.3 Simple I
2
C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21)
This is a function that synchronizes clock communication with multiple devices through a total of 2 lines of
serial clock (SCL) and serial data (SDA). Because this simple I2C is designed for single communication with
EEPROM, flash memory, A/D converters, etc., it is only used as a master device.
For start and stop conditions, AC specifications must be adhered to and processed by software while
operating the control registers. For specific setup examples, refer to 12.9 Simplified I2C (IIC00, IIC01, IIC10,
IIC11, IIC20, IIC21) communication operation.
[Transmit and receive data]
 Master sending, master receiving (limited to single master control functions).
 ACK output function
Note
, ACK detection function
 8 bits of data length (when sending the address, specify the address with a high 7 bits, and use the
lowest bit for R/W control).
 Manual generation of start and stop conditions
[Interrupt function]
 End of transfer interruption
[Error detection flag]
 ACK error, overflow error.
※[Features not supported by Simplified I
2
C]
 Slave send, slave receive
 Quorum failure detection function
 Wait for detection function
Note When receiving the last data, if you write 0 to the SOEmn bit (serial output enable register m (SOEm)) to stop
the output of the serial communication data, the ACK is not output. For details, please refer to 12.9.3 Processing
Flow.
Note When using the full-featured I
2
C-bus, refer to Chapter 14, Serial Interface IICA.