CMS32L051 User Manual |Chapter 18 Interrupt Function
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18.3 Registers controlling interrupt function
The interrupt function is controlled by the following four registers.
Interrupt request flag register (IF00~IF31).
Interrupt mask flag register (MK00~MK31).
External interrupt rising edge enable register (EGP0).
External interrupt falling edge enable register (EGN0).
18.3.1 Interrupt request flag registers (IF00 to IF31)
By incurring a corresponding interrupt request or executing instructions, the interrupt request flag is set to
1.
By generating a reset signal or executing an instruction, the interrupt request flag is clear to 0.
The IF00L to IF31L registers are set via 8-bit memory operation instructions
Or set the IF00~IF31 registers via 32-bit memory operation instructions.
After the reset signal is generated, the values of these registers become 00 00_0000H.
Figure 18-2 Format of interrupt request flag register (IFm) (m=0~31)
address:IF00:40006000H,IF01:40006004H,IF02:40006008H,IF03:4000600CH
IF04:40006010H,IF05:40006014H,IF06:40006018H,IF07:4000601CH
IF08:40006020H,IF09:40006024H,IF10:40006028H,IF11:4000602CH
IF12:40006030H,IF13:40006034H,IF14:40006038H,IF15:4000603CH
IF16:40006040H,IF17:40006044H,IF18:40006048H,IF19:4000604CH
IF20:40006050H,IF21:40006054H,IF22:40006058H,IF23:4000605CH
IF24:40006060H,IF25:40006064H,IF26:40006068H,IF27:4000606CH
IF28:40006070H,IF29:40006074H,IF30:40006078H,IF31:4000607CH
Reset value: 0000_0000HR/W
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