Cmsemicon CMS32L051 - IICA Low Level Width Setting Register N (Iicwln); IICA High Level Width Setting Register N (Iicwhn)

V1.2.2
CMS32L051 User Manual |Chapter 14 Serial interface IICA
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14.3.6 IICA low level width setting register n (IICWLn)
This register controls the SCLAn pin signal low width (tLOW) and the SDAAn pin signal of the serial
interface IICA output.
The IICWLn register is set via an 8-bit memory operation command.
It is necessary to run at bit7 (IICEn) at I
2
C (IICCn) running (IICA control register n0 (IICCTLn0)) = 0) when
the IICWLn register is set. After the reset signal is generated, the value of this register changes to FFH.
For information on how to set the IICWLn registers, refer to 14.4.2Setting the transmit clock via IICWLn
register and IICWHn register
The data retention time is 1/4 of the time set by IICWLn.
Figure 14-10 Format of IICA low-level width setting register n (IICWLn)
Address: 0x40041A32 After reset: FFHR/W
Symbol
7 6 5 4 3 2 1 0
IICWLn
14.3.7 IICA high level width setting register n (IICWHn)
This register controls the SCLAn pin signal high width and SDAAn pin signal of the serial interface IICA
output. The IICWHn register is set via an 8-bit memory operation command.
The IICWHn register must be set when I2C operation is disabled (bit7(IICEn)=0 of IICA control register
n0(IICCTLn0)). After a reset signal is generated, the value of this register becomes "FFH".
Figure 14-11 Format of high level width setting register n(IICWHn)
Address: 0x40041A33 After reset: FFHR/W
Symbol
7 6 5 4 3 2 1 0
IICWHn
Remark 1. For the setting method of the master controller transmission clock, please refer to 14.4.2(1); For the method of
setting the slave IICWLn register and the IICWHn register, refer to14.4.2).
2.n=0