Cmsemicon CMS32L051 - 20.2 Sleep mode

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CMS32L051 User Manual |Chapter 20 Standby Function
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20.2 Sleep mode
20.2.1 Setting of the sleep mode
When the SLEEPDEEP bit of the SCR register is 0, the WFI instruction is executed and sleep mode is entered.
In sleep mode, the CPU stops operating, but the values of the internal registers are still maintained and peripheral
modules remain in the state they were in before they entered sleep mode. The status of peripheral modules,
oscillators, etc. in sleep mode is shown in Table 20-1
Sleep mode can be set regardless of whether the CPU clock before setting is a high-speed system clock, a
high-speed internal oscillator clock, or a subsystem clock.
Note When the interrupt mask flag is 0 (allow interrupt processing) and the interrupt request flag is 1 (generating
an interrupt request signal), the interrupt request signal is used to release sleep mode. Therefore, even when
WFI instructions are performed in this case, it is not transferred to sleep mode.
Table 20-1 Operation status in sleep mode (1/2)
Setting of the sleep
mode
Item
Execution of WFI instructions while the CPU is running at the main system clock
CPU with high speed internal
oscillator clock (F
IH
) run
CPU runs on X1 clock (f
X
).
CPU with external master
system clock (F
EX
) run
System clock
Stop supplying clocks to the CPU.
Main system
clock
f
IH
Continue to run (cannot be
stopped).
Disable operation.
f
X
Disable operation.
Continue to run (cannot be
stopped).
Cannot run.
f
EX
Cannot run.
Continue to run (cannot be
stopped).
Subsystem
Clock
f
XT
Remains in the state it was in before it was set to sleep mode.
f
EXS
Low-speed
internal
oscillation
Clock of the
device
f
II
Bit0 (WDSTBYON) and bit4 (WDTON) and the secondary system clock via option bytes
(000C0H) are available
Allows the WUTMMCK0 bit of the mode control register (OSMC) to be set.
WUTMMCK0=1: Oscillation
WUTMMCK0=0 and WDTON=0: Stop
WUTMMCK0=0, WDTON=1 and WDSTBYON=1:
Oscillation
WUTMMCK0=0, WDTON=1 and WDSTBYON=0: Stop
CPU
Stop running.
Code flash
RAM
Stop running (can run when DMA is executed).
Port (latch)
Remains in the state it was in before it was set to sleep mode.
Universal timer unit
Can run.
Real-time clock (RTC).
1 5-bit interval timer
Watchdog timer
See Chapter 10: Watchdog Timer.
Clock output/buzzer output
Can run.
A/D converter
Universal Serial
Communication Unit (SCI).
Serial Interface (IICA).
Data Transfer Controller
(DMA).
Linkage controller
Links can be made between runnable function blocks.
Power-on reset function
Can run.
Voltage detection function
External interrupts
CRC
operation
High-speed
CRC