CMS32L051 User Manual |Chapter 10 Watchdog Timer
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10.4 Operation of the watchdog timer
10.4.1 Operational control of the watchdog timer
1. When using the watchdog timer, set the following via option bytes (000C0H):
The bit4 (WDTON) of option byte (000C0H) must be set to 1 to enable the watchdog
timer's count to run (after the reset is released, the counter starts running) (see Section 1
Chapter 26 Option Byte for details).
The overflow time must be set by bit3~1 (WDCS2~WDCS0) of option bytes (000C0H) (refer to
Section 10.4.2 and Chapter 26).
WINDOW0) (see for details Section 10.4.2 and Chapter 26).
2. After the reset is released, the watchdog timer starts counting.
3. After starting the count and before the overflow time set by the option byte, if you write ACH to
the allowed register (WDTE) of the watchdog timer, clear the watchdog timer and restart the
count.
4. After that, the write operation of the WDTE register after the second time after the reset is
released must be performed during the window open. If the WDTE register is written during
window shutdown, an internal reset signal is generated.
5. If the overflow time is exceeded by not writing ACH to the WDTE
register, an internal reset signal is generated. An internal reset signal
is generated in the following cases:
When performing bit manipulation instructions on WDTE registers
When writing data other than ACH to the WDTE register
Note 1 Only when the allowed register (WDTE) of the watchdog timer is written for the first time after the reset is
released, regardless of the window opening period, as long as the WDTE is written at any time before the overflow
time, the watchdog timer is cleared and the count is restarted.
2. From writing ACH to the WDTE register to clearing the counter of the watchdog timer, it is possible to generate
an error of up to 2 f-IL clocks.
3. Before the overflow of the count value, the watchdog timer can be cleared.
4. As shown below, the operation of the watchdog timer in sleep or deep sleep mode varies depending on the setting
value of bit0 (WDSTBYON) of the option byte (000C0H).
When the WDSTBYON bit is 0, the watchdog timer counts are restarted after the sleep or deep sleep mode is
released. At this point, clear the counter to 0 and start counting.
When the X1 oscillation clock is run after the deep sleep mode is released, the CPU starts running after the oscillation
stabilization time.
If the time from the release of the deep sleep mode to the overflow of the watchdog timer is short, the watchdog
overflow occurs within the oscillation stabilization time and a reset occurs. Therefore, if you want to run with the X1
oscillation clock and clear the watchdog timer after the interval interrupt is released from the deep sleep mode, since the
watchdog timer is not cleared after the oscillation settling time, this situation must be considered for the setting of the
overflow time.
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