CMS32L051 User Manual |Chapter 14 Serial interface IICA
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14.5.7 Release method of wait
In general, I
2
C can release the wait with the following processing.
IICA shift register n (IICAn).
Set bit5 (WRELn) of IICA control register n0 (IICCTLn0) (wait release).
Set bit1 (STTn) of the IICCTLn0 register (generate start condition)
Note
.
Set bit0 (SPTn) of the IICCTLn0 register (generate stop condition)
Note
.
Note: Only for the master control device.
If these wait releases handling is performed, I2C releases the wait and resumes communication. To send
data (including addresses) after release wait, data must be written to the IICAn register.
To receive data after released wait or to end sending data, bit5 (WRELn) of the IICCTLn0 register must
be set to 1. To generate a restart condition after release wait, bit1 (STTn) of the IICCTLn0 register must be
set to 1. To generate a stop condition after release wait, bit0 (SPTn) of the IICCTLn0 register must be set to
1. Release processing can only be performed once for one wait.
For example, if data is written to the IICAn register after release wait by removing the wait at the WRELn
is 1, the timing of the change in the SDAAn line may conflict with the write timing of the IICAn register,
resulting in the wrong value being output to SDAAn line. In addition to these processing, in the case of a
neutral stop of communication, if the IICEn bit is cleared to 0, the communication is stopped, so the wait can
be releaseed. In the case where the I2C-bus state is deadlocked due to noise, if bit6 (LRELn) of the IICCTLn0
register is set 1, the communication is exited, so the wait can be released.
Note If the pending dismissal process is performed when the
WUPn bit is 1, the wait is not released.
Remark n=0
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