Cmsemicon CMS32L051 - Page 507

V1.2.2
CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-19 Wait (2/2)
(2) The case where both the master and slave devices are waiting for 9 clocks
(Master device: send, slave device: receive, ACKEn=1).
master device and
slave device all enter
into wait state after
output 9th clock.
write data into IICAn (release
from wait).
IICAnFFH or WRELn1
slave device waits
master device
and slave
device both wait
H
IICAn
SCLAn
SCLAn
IICAn
ACKEn
SCLAn
SDAAn
transmis
sion line
slave
device
master
device
generates according to pre-configured ACKEn.
Note ACKEn: bit2 of IICA control register n0
(IICCTLn0).
WRELn: Bit5 of IICA control register n0
(IICCTLn0).
The wait state is automatically generated by setting bit3 (WTIMn) of IICA control register n0 (IICCTLn0).
Typically, on the receiver, if bit5 (WRELn) of the IICCTLn0 register is 1 or if the IICA shift register is given n
(IICAn) writes FFH and releases the wait; On the sender, if data is written to the IICAn register, the wait is
released. The master device can also unwait in the following ways:
• Set bit1 (STTn) of the IICCTLn0 register to 1.
• Set bit0 (SPTn) of the IICCTLn0 register to 1.
Note n=0