Cmsemicon CMS32L051 - Subsystem Clock Supply Mode Control Register (OSMC)

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CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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4.3.7 Subsystem clock supply mode control register (OSMC)
OSMC registers are registers that reduce power consumption by stopping unwanted clock functions.
If RTCLPC bit set to 1, it stops providing clock to peripheral functions other than the real-time clock and
15-bit interval timer in deep sleep mode or sleep mode where the CPU runs on the subsystem clock, thus
reducing power consumption.
In addition, the real-time clock and the operating clock of a 15-bit interval timer can be selected through
the OSMC register.
OSMC registers are set via 8-bit memory operation instructions.
After the reset signal is generated, the value of this register becomes 00H.
Figure 4-9 Format of subsystem clock supply mode control register (OSMC)
Address: 40020423H After reset: 00H R/W
Symbol
7 6 5 4 3 2 1 0
OSMC
RTCLPC
The settings in deep sleep mode and sleep mode where the CPU runs at the subsystem
clock
0
Allows the subsystem clock to be supplied to peripheral functions
(For peripheral functions that are allowed to operate, please refer to Table 19-1 to Table 19-
3.)
1
Stop supplying the subsystem clock for the real-time clock and peripheral functions other
than the 15-bit interval timer.
WUTMMCK0
Selection of the operating clock for the real-time clock, 1-5-bit interval
timer
0
ubsystem clock is the real-time clock and the operating clock of the 1 5-bit interval
timer.
1
-speed internal oscillator clock is the operating clock of the real-time clock and the
15-bit interval timer.
RTCLPC
0
0
WUTMMCK0
0
0
0
0