CMS32L051 User Manual |Chapter 14 Serial interface IICA
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14.2 Structure of the serial interface IICA
The serial interface IICA consists of the following hardware.
Table 14-1 Structure of serial Interface IICA
Peripheral enable register 0 (PER0).
IICA control register n0 (IICCTLn0).
IICA status register n (IICSn).
IICA flag register n (IICFn).
IICA control register n1 (IICCTLn1).
IICA low width setting register n (IICWLn)
IICA high width setting register n(IICWHn).
Port mode register (PMxx).
Port mode control register (PMCxx).
Port multiplexing function configuration register (PxxCFG).
Note 1. n = 0.
2. This product can multiplex the IICA input/output pin function to any port. When a port is configured as a multiplexed
function of the IICA pin, the N-channel open-drain output (V
DD
/EV
DD
withstand voltage) mode of the port is guaranteed to open
automatically by design, i.e. the POMxx register does not require user settings.
(2)
IICA shift register n (IICAn)
IICAn registers are registers that convert 8-bit serial data and 8-bit parallel data to and from the serial
clock for transmission and receiving. The actual transmitting and receiving can be controlled by reading and
writing IICAn registers.
During the wait, the wait is released by writing the IICAn register and the data transfer begins. The IICAn
register is set via an 8-bit memory operation instruction. After the reset signal is generated, the value of this
register becomes 00H.
Figure 14-3 Format of IICAn shift register n (IICAn)
Address: 0x40041B50 After reset: 00HR/W
Symbol
7 6 5 4 3 2 1 0
IICAn
Note 1 During data transfer, data cannot be written to the IICAn register.
2. IICAn registers can only be read and written while waiting. Access to IICAn registers in a communication state is
prohibited except during the waiting period. However, in the case of a master device, the IICAn register can be
written once after the communication trigger bit (STTn) is set to 1.
3. When scheduling communication, data must be written to the IICAn register after detecting an interrupt caused by a
stop condition.
Note n=0
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