Cmsemicon CMS32L051 - Timer Status Register Mn (Tsrmn)

V1.2.2
CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.3.4 Timer status register mn (TSRmn)
The TSRmn register is a register that represents the overflow status of the channel n counter.
The TSRmn register is only valid in capture mode (MDmn3 to MDmn1=010B) and capture & single count
mode (MDmn3 to MDmn1=110B). Refer to Table 5-4 for the change of OVF bits and the set/clear conditions in
each operation mode.
The TSRmn register is read through 16-bit memory operation instructions.
The lower 8 bits of the TSRmn register can be read with TSRmnL and via 8-bit memory operation
instructions. After the reset signal is generated, the value of the TSRmn register changes to 0000H.
Figure 5-13 Table of timer status register mn (TSRmn)
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSRmn
OVF
Counter overflow status of channel n
0
No overflow occurred.
1
Overflow occurs.
If the OVF bit is 1, this flag is cleared the next time the count does not overflow and the count value is
snapped (OVF=0).
Note m: Unit number (m=0, 1) n: channel number (n=0~3).
Table 5-4 OVF bit change and set/clear conditions in each operating mode
Timer operating mode
OVF bit
Set/clear conditions

 & Single Count mode
Clear
No overflow occurred at the time of capture
Set
An overflow occurs during capture



Clear

(Cannot be used)
Set
Remark: Even if the counter overflows, the OVF bit does not change immediately and changes at capture thereafter.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OVF