CMS32L051 User Manual |Chapter 16 Enhanced DMA
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16.4 DMA operation
Once the DMA is started, the control data is read from the DMA control data area, the data is transmitted
according to this control data, and the control data after the data transmission is written back to the DMA
control data area. It can save 24 groups of control data to the DMA control data area and transfer 24 groups of
data. There are normal and repeat modes in the transfer mode, and the transfer sizes are 8-bit transfer, 16-bit
transfer, and 32-bit transfer. When the CHNE bit of the DMACRj(j=0~23) register is 1 (chain transfer enable),
1 passes The initiation source reads multiple control data for continuous data transfer (chain transfer).
The transmit source address and the transmit destination address are specified through the 32-bit
DMSARj register and the 32-bit DMDARj register, respectively. After data transfer, the values of the DMSARj
register and the DMDARj register are incremented or fixed according to the control data.
16.4.1 Start the source
The DMA is initiated by the interrupt signal of the peripheral function, and the interrupt signal to start the
DMA is selected through the DMAENi (i=0~2) register. When the data transmission (in the case of chain
transmission, continuous initial transmission) is set to the DMAENi0~DMAENi7 bits of the corresponding
DMAENi register in the DMA operation "0" (disables startup).
In normal mode, a DMACTj (j=0~23) register is transferred to "0".
In repeat mode, the RPTINT bit of the DMACRj register is 1 (interrupts are enable) and the
DMACTj register is transferred to 0.
The internal operation flowchart of DMA is shown in Figure 16-14.
Figure 16-14 Flowchart of DMA internal operation
DMA start source triggers
read vector
branch (1)
CHNE=1？
Yes
No
Yes
No
transmit data
read control data
CHNE=1？
No
end
Yes
write '0' to
DMAENi0~DMAENi7 bits,
generate interrupt request
write back control data
CHNE=1？
write back control data
write back control data
transmit data
read control data
transmit data
read control data
CHNE=1？
No
Yes
write back control data
end
No
Yes
(note)
branch (1)
If it is following condition, then interrupt request generates after DMAENi0 ~ DMAENi7
bit are written with '0'.
in normal mode, perform DMACTj(j=0~23) register from '1' to '0' transfer.
In repeat mode, RPTINT bit as '1' and perform DMACTj register from '1' to '0' transfer.
Remark:
DMAENi0~DMAENi7：DMAENi(i=0~4)register bit
RPINT，CHNE：DMACRj(j=0~23) register bits
interrupt handling
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