Cmsemicon CMS32L051 - Timer Interrupt and Tomn Pin Output When Counting Starts

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CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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5.6.5 Timer interrupt and TOmn pin output when counting starts
In interval timer mode or capture mode, the MDmn0 bit of the timer mode register mn (TMRmn) is
the bit that sets whether a timer interrupt is generated at the start of the count.
When the MDmn0 bit is 1, the start timing of the count can be known by generating a timer
interrupt (INTTMmn). In other modes, the timer interrupt at start count and the TOmn output are not
controlled. An example of operation when set to interval timer mode (TOEmn=1, TOMmn=0) is shown
below.
Figure 5-39 Running example of timer interrupt and TOmn output at the start of counting
(a) When the MDmn0 bit is 1
TCRmn
TEmn
INTTMmn
TOmn
Start counting
(b) When the MDmn0 bit is 0
TCRmn
TEmn
INTTMmn
TOmn
Start counting
When the MDmn0 bit is 1, the timer interrupt (INTTMmn) is output at the start of the count and the TOmn
is output alternately.
When the MDmn0 bit is 0, the timer interrupt (INTTMmn) is not output at the beginning of the count and
the TOmn does not change, while the INTTMmn is output after counting 1 cycle and TOmn is output
alternately.
Note m: Unit number (m=0, 1) n: channel number (n=0~3).