Cmsemicon CMS32L051 - Peripheral Enable Register 0 (PER0)

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.3.1 Peripheral enable register 0 (PER0).
The PER0 register is a register that sets the clock to be allowed or disallowed to be supplied to each
peripheral hardware. Reduce power consumption and noise by stopping clocking unused hardware.
To use universal serial communication unit 0, bit2 (SCI0EN) must be set to 1.
To use universal serial communication unit 1, bit3 (SCI1EN) must be set to 1.
The PER0 register is set via an 8-bit memory operation command.
After the reset signal is generated, the value of the PER0 register changes to 00H.
Figure 12-5 Format of peripheral enable register 0 (PER0)
Address: 0x40020420
After reset: 00H
R/W
symbol
7
6
5
4
3
2
1
0
PER0
RTCEN
GODAEN
ADCEN
IICA0EN
SCI1EN
SCI0EN
TM41IN
TM40EN
SCImEN
Provides control of the input clock of the universal serial communication unit m
0
Stop supplying the input clock.
 m using SFR.
 m is in a reset state.
1
Allows the input clock to be provided.
 m used.
Note 1 To set the universal serial communication unit m, the following registers must first be set in the S CImEN bit 1.
When the SCImEN bit is 0, the write operation of the control register of the universal serial communication unit
m is ignored, and the read value is the initial value (input switch control register (ISC), The noise filter allows
register 0 (NFEN0), the port multiplexing function configuration register (Px xCFG), and the port output mode
register ( POMx), port mode registers (PMx), port mode control registers (PMCx), and port registers (Px).
 m (SPSm).
 mn (SMRmn).
operation setting register mn (SCRmn).
 mn (SDRmn).
 mn (SIRmn).
 mn (SSRmn).
 m (SSm).
 m (STm).
enable status register m (SEm).
enable register m (SOEm).
 m (SOLm).
 m (SOm).