CMS32L051 User Manual |Chapter 16 Enhanced DMA
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16.5.3 Number of execution clocks for DMA
The execution and number of clocks required at DMA startup are shown in Table 16-9.
Table 16-9 Execution and number of clocks required when DMA is started
Note 1. For the number of clocks required to write back control data, refer to Table 16-10 Number of clocks required to write
back control data
2. For the number of clocks required to read and write data, please refer to Table 16-11 Number of clocks required to read
and write data
Table 16-10 Number of clocks required to write back control data
Setting of the DMACR register
Controls the write-back of registers
Note j=0~23, X: 0 or 1
Table 16-11 Number of clocks required to read and write data
Special function
registers
(SFR)
Extended Special Function Register (2ndSFR)
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