Cmsemicon CMS32L051 - Serial Clock Select Register M (Spsm)

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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12.3.2 Serial clock select register m (SPSm)
The SPSm register is a 16-bit register that selects two common operating clocks (CKm0, CKm1) available
to each channel. CKm1 is selected by bit7~4 of the SPSm register, and by bit3~0 CKm0.
It is forbidden to overwrite the SPSm register during operation (SEmn=1).
The SPSm register is set via 16-bit memory operation instructions.
I can set the low 8 bits of the SPSm register with SPSmL and via 8-bit memory operation instructions.
After the reset signal is generated, the value of the SPSm register changes to 0000H.
Figure 12-6 Format of serial clock selection register m (SPSm)
Address: 40041126H (SPS0), 40041566H (SPS1) after reset: 0000HR/W
Symbol
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPSm
PRSmk3
PRSmk2
PRSmk1
PRSmk0
Selection of the operating clock
(CKmk)
Note
0
0
0
0
f
CLK
0
0
0
1
f
CLK
/2
0
0
1
0
f
CLK
/2
2
0
0
1
1
f
CLK
/2
3
0
1
0
0
f
CLK
/2
4
0
1
0
1
f
CLK
/2
5
0
1
1
0
f
CLK
/2
6
0
1
1
1
f
CLK
/2
7
1
0
0
0
f
CLK
/2
8
1
0
0
1
f
CLK
/2
9
1
0
1
0
f
CLK
/2
10
1
0
1
1
f
CLK
/2
11
1
1
0
0
f
CLK
/2
12
1
1
0
1
f
CLK
/2
13
1
1
1
0
f
CLK
/2
14
1
1
1
1
f
CLK
/2
15
Note To change the clock selected as f
CLK
(change the value of the system clock control register (CKC)) during the
operation of the Universal Serial Communication Unit (SCI), the operation of the SCI must be stopped (serial
channel stop register m (STm)=000FF) and then make the change.
Note Bit15~8 must be set to 0.
Note 1. f
CLK
: Clock frequency of the CPU/peripheral hardware
2. m: Unit number (m=0, 1).
3. k=0, 1
0
0
0
0
0
0
0
0
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00