Cmsemicon CMS32L051 - 11.4 Operation mode of A;D converter

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CMS32L051 User Manual |Chapter 11 A/D Converter
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11.4 Operation mode of A/D converter
The operation of each mode of the A/D converter is as follows. For the setting steps for each mode, refer
to Setup Flow Diagram of 11.5 A/D Converter.
11.4.1 Software trigger mode (select mode, continuous conversion mode)
(1) In the stop state, the ADCE bit of the mode register 0 (ADM0) of the A/D converter is 1 and enters
the A/D transition standby state.
(2) After counting the stable wait time (1 us) by software, the ADCS bit of the ADM0 register is 1 for the
register specified by the analog input channel (ADS) specifies the analog input for A/D conversion.
(3) If the A/D conversion ends, the conversion results are saved to the A/D conversion result register
(ADCR, ADCRH) and an A/D conversion end interrupt request signal (INTAD) is generated). Start the
next A/D conversion immediately after the A/D conversion ends.
(4) If you override the 1 to the ADCS bit during the conversion, the current A/D conversion is aborted
immediately and the conversion begins again.
(5) If the ADS registers are overwritten or rewritten during the conversion, the current A/D conversion is
aborted immediately, and then the analog inputs respecified by the ADS registers are A/D.
(6) The A/D conversion does not start even if the input hardware triggers during the conversion.
(7) If the ADCS bit is 0 during the conversion, the current A/D conversion is aborted immediately and
then enters the A/D transition standby.
(8) If the ADCE bit is 0 in the A/D transition standby state, the A/D converter enters a stopped state.
When the ADCE bit is 0, even the ADCS set to 1 is ignored and the A/D conversion is not started.
Figure11-16 Timing example of software trigger mode (select mode, continuous conversion mode)
set 1 to ADCE bit
set ADCS bit to 1 during
conversion idle state
start next cnversion when A/
D conversion completes
auto restart
conversion when
conversion
completes
auto restart
conversion when
conversion
completes
conversion
stops
rewrite ADCS bit to 1 during
A/D conversion operation
generate hardware trigger
(be ignored) during A/D
conversion operation
clear ADCS bit
to 0 during
conversion
modify ADS (from ANI0 to
ANI1) during A/D conversion
clear ADCS bit to 0
A/D conversion
state
stop
converting
idle
conversion
stop
converting
idle
conversion